1. Field of the Invention
The present invention relates to the extraction of a recovered clock signal from an incoming data bit stream received from a communications system and, in particular, to a device and method for measuring the jitter of the recovered clock signal.
2. Description of the Related Art
A clock synchronizer is a device that generates a recovered clock signal from an incoming data bit stream received from a communications system. The recovered clock signal is typically generated by a process, known as a "look-and-predict" technique, which produces a set of long-term timing statistics from the incoming data bit stream and then generates the recovered clock signal based on the timing statistics. Ideally, the recovered clock signal is generated so that a close phase agreement exists between the incoming data bit stream and the recovered clock signal.
The term "close phase agreement" defines a detection position within each bit cell of the incoming data bit stream, which is known as the center of the signal eye, at which the active edges of the recovered clock signal should be located. The amount of unwanted phase movement of the recovered clock signal away from the detection position is defined as the jitter of the recovered clock signal. Jitter, which is measured over a long period of time, is by definition a statistical measurement.
The "look-and-predict" technique, as described above, can introduce jitter into the recovered clock signal due to differences between the instantaneous timing of the incoming bit stream and the long-term timing statistics. Clock jitter is harmful because jitter increases symbol detection errors and, consequently, transmission errors. Thus, to accurately predict the performance of a digital communication system, there is a need to measure the jitter of the recovered clock signal.
Conventionally, jitter is measured utilizing either a digital oscilloscope or a Bit Error Rate Tester (BERT). The digital oscilloscope provides a fast and interactive method for measuring jitter. However, it often produces underestimates of the actual amount of jitter. The BERT, on the other hand, is a slow and non-interactive method, but offers very precise jitter limit measurements.
Both of these methods require access to the recovered clock signal so that clock timing information can be extracted. In the case of the digital oscilloscope, recovered clock edges are translated into time displacement image vectors. An accumulation of these image vectors produces a statistical display of the jitter values on the oscilloscope screen.
The statistical display, however, may not show the actual peak-to-peak jitter value of the recovered clock signal because digital oscilloscopes, which trace the recovered clock signal, require a very long processing time after each trace. During the processing periods, the clock jitter readings are ignored and not displayed.
In the case of the BERT, recovered clock edges are translated into binary error counts, i.e., only errors and non-errors are recorded. Since the results contain no quantified time values, users must run repeated tests to obtain a full jitter distribution chart.
Thus, there is a need for a device and method for measuring jitter which provides fast, interactive, and precise jitter measurements, and which minimizes the external test system required to extract the jitter measurements.
The jitter requirements for a clock synchronizer utilized in a Fiber Distributed Data Interface (FDDI) network is specified by the "System Jitter Allocation Budget for Guaranteed Interconnections" section of the Draft Proposed American National Standard on "FDDI Physical Layer Medium Dependent (PMD) document", X3T9.5/84-48, May 20, 1988.
The FDDI network provides a high bandwidth interconnection among computers and peripheral equipment using fiber optics as the transmission media. The symbols are transmitted synchronously, at a rate of 125 Mega-symbols per second. The modulation scheme is Non-Return-to-Zero Inverted (NRZI) with a nominal symbol period of 8 nSec (nanoseconds).
An optical receiver is used to convert the FDDI optical symbol stream to an electrical signal. After the conversion, the symbol information is detected by a detector circuit which receives timing information from a clock synchronizer. As described above, the clock synchronizer, based on the symbol timing history, creates a recovered clock signal which is fed back to the detector circuit.
If there are no imperfections introduced along the transmission path (including the optical to electrical conversion), a maximum "signal eye opening" of 8 nSec would be expected at the inputs of the clock synchronizer and the symbol detector. However, there are many types of imperfections and interferences affecting the incoming signal quality during the transmission. For these reasons, the FDDI standard committee has proposed a jitter budget for guiding the development of the FDDI optical receiver so that better equipment interoperability can be achieved.
The budget recommendation is based on a requirement that any FDDI station shall not exceed a bit error rate of 2.5.times.10.sup.-10 under any conditions that meet the FDDI proposed standards. A condensed outline from the jitter budget is as follows:
a. The signal at the input of the clock synchronizer may contain the following types of imperfections:
Duty Cycle Distortion (DCD) PA1 Data Dependent Jitter (DDJ) PA1 Random Jitter (RJ) PA1 The combination of all these imperfections shall not exceed 5.9 nsec peak-to-peak. This translates to a minimum "eye opening" of 2.1 nsec (8-5.9=2.1 nsec) measured at the inputs of the clock synchronizer and the symbol detector.
b. In order to achieve the specified bit error rate (2.5.times.10.sup.-10), the jitter of the recovered clock shall be kept below 3.3 nsec peak-to-peak. The reason this value (3.3 nSec) can exceed the "signal eye opening" of 2.1 nsec is some components of the two jitter values (jitter generated from the clock synchronizer and the jitter value measured at the synchronizers input) are considered to be uncorrelated (i.e., the total budget from the nominal symbol period of 8 nsec is divided down into component-vectors, uncorrelated vectors are summed vectorially and the algebraic sum of all the quantities is 8 nsec).
For a well-designed FDDI clock synchronizer, the jitter of the recovered clock signal is around 0.5 to 1.5 nSec peak-to-peak. The remaining margin (3.3-1.5 nSec) is reserved for the static alignment error (SAE) and other imperfections. Thus, in order to obtain reliable jitter measurements in accordance with the FDDI specification, there is a need for a device and method for measuring jitter which provides a phase resolution of 100 pSec (picoseconds) or better.